|
|
|
1 |
From d377918c23d85f64d01914b43bfabc0a46fe974a Mon Sep 17 00:00:00 2001 |
2 |
From: Gerd Hoffmann <kraxel@redhat.com> |
3 |
Date: Tue, 26 Apr 2016 15:24:18 +0200 |
4 |
Subject: [PATCH 3/5] vga: factor out vga register setup |
5 |
|
6 |
When enabling vbe mode qemu will setup a bunch of vga registers to make |
7 |
sure the vga emulation operates in correct mode for a linear |
8 |
framebuffer. Move that code to a separate function so we can call it |
9 |
from other places too. |
10 |
|
11 |
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> |
12 |
Signed-off-by: Stefano Stabellini <sstabellini@kernel.org> |
13 |
--- |
14 |
hw/display/vga.c | 79 +++++++++++++++++++++++++++++++------------------------- |
15 |
1 file changed, 44 insertions(+), 35 deletions(-) |
16 |
|
17 |
diff --git a/hw/display/vga.c b/hw/display/vga.c |
18 |
index da1eb4a..cf5f97e 100644 |
19 |
--- a/hw/display/vga.c |
20 |
+++ b/hw/display/vga.c |
21 |
@@ -673,6 +673,49 @@ static void vbe_fixup_regs(VGACommonState *s) |
22 |
s->vbe_start_addr = offset / 4; |
23 |
} |
24 |
|
25 |
+/* we initialize the VGA graphic mode */ |
26 |
+static void vbe_update_vgaregs(VGACommonState *s) |
27 |
+{ |
28 |
+ int h, shift_control; |
29 |
+ |
30 |
+ if (!vbe_enabled(s)) { |
31 |
+ /* vbe is turned off -- nothing to do */ |
32 |
+ return; |
33 |
+ } |
34 |
+ |
35 |
+ /* graphic mode + memory map 1 */ |
36 |
+ s->gr[VGA_GFX_MISC] = (s->gr[VGA_GFX_MISC] & ~0x0c) | 0x04 | |
37 |
+ VGA_GR06_GRAPHICS_MODE; |
38 |
+ s->cr[VGA_CRTC_MODE] |= 3; /* no CGA modes */ |
39 |
+ s->cr[VGA_CRTC_OFFSET] = s->vbe_line_offset >> 3; |
40 |
+ /* width */ |
41 |
+ s->cr[VGA_CRTC_H_DISP] = |
42 |
+ (s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 3) - 1; |
43 |
+ /* height (only meaningful if < 1024) */ |
44 |
+ h = s->vbe_regs[VBE_DISPI_INDEX_YRES] - 1; |
45 |
+ s->cr[VGA_CRTC_V_DISP_END] = h; |
46 |
+ s->cr[VGA_CRTC_OVERFLOW] = (s->cr[VGA_CRTC_OVERFLOW] & ~0x42) | |
47 |
+ ((h >> 7) & 0x02) | ((h >> 3) & 0x40); |
48 |
+ /* line compare to 1023 */ |
49 |
+ s->cr[VGA_CRTC_LINE_COMPARE] = 0xff; |
50 |
+ s->cr[VGA_CRTC_OVERFLOW] |= 0x10; |
51 |
+ s->cr[VGA_CRTC_MAX_SCAN] |= 0x40; |
52 |
+ |
53 |
+ if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) { |
54 |
+ shift_control = 0; |
55 |
+ s->sr[VGA_SEQ_CLOCK_MODE] &= ~8; /* no double line */ |
56 |
+ } else { |
57 |
+ shift_control = 2; |
58 |
+ /* set chain 4 mode */ |
59 |
+ s->sr[VGA_SEQ_MEMORY_MODE] |= VGA_SR04_CHN_4M; |
60 |
+ /* activate all planes */ |
61 |
+ s->sr[VGA_SEQ_PLANE_WRITE] |= VGA_SR02_ALL_PLANES; |
62 |
+ } |
63 |
+ s->gr[VGA_GFX_MODE] = (s->gr[VGA_GFX_MODE] & ~0x60) | |
64 |
+ (shift_control << 5); |
65 |
+ s->cr[VGA_CRTC_MAX_SCAN] &= ~0x9f; /* no double scan */ |
66 |
+} |
67 |
+ |
68 |
static uint32_t vbe_ioport_read_index(void *opaque, uint32_t addr) |
69 |
{ |
70 |
VGACommonState *s = opaque; |
71 |
@@ -759,53 +802,19 @@ void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val) |
72 |
case VBE_DISPI_INDEX_ENABLE: |
73 |
if ((val & VBE_DISPI_ENABLED) && |
74 |
!(s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED)) { |
75 |
- int h, shift_control; |
76 |
|
77 |
s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = 0; |
78 |
s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0; |
79 |
s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0; |
80 |
s->vbe_regs[VBE_DISPI_INDEX_ENABLE] |= VBE_DISPI_ENABLED; |
81 |
vbe_fixup_regs(s); |
82 |
+ vbe_update_vgaregs(s); |
83 |
|
84 |
/* clear the screen (should be done in BIOS) */ |
85 |
if (!(val & VBE_DISPI_NOCLEARMEM)) { |
86 |
memset(s->vram_ptr, 0, |
87 |
s->vbe_regs[VBE_DISPI_INDEX_YRES] * s->vbe_line_offset); |
88 |
} |
89 |
- |
90 |
- /* we initialize the VGA graphic mode (should be done |
91 |
- in BIOS) */ |
92 |
- /* graphic mode + memory map 1 */ |
93 |
- s->gr[VGA_GFX_MISC] = (s->gr[VGA_GFX_MISC] & ~0x0c) | 0x04 | |
94 |
- VGA_GR06_GRAPHICS_MODE; |
95 |
- s->cr[VGA_CRTC_MODE] |= 3; /* no CGA modes */ |
96 |
- s->cr[VGA_CRTC_OFFSET] = s->vbe_line_offset >> 3; |
97 |
- /* width */ |
98 |
- s->cr[VGA_CRTC_H_DISP] = |
99 |
- (s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 3) - 1; |
100 |
- /* height (only meaningful if < 1024) */ |
101 |
- h = s->vbe_regs[VBE_DISPI_INDEX_YRES] - 1; |
102 |
- s->cr[VGA_CRTC_V_DISP_END] = h; |
103 |
- s->cr[VGA_CRTC_OVERFLOW] = (s->cr[VGA_CRTC_OVERFLOW] & ~0x42) | |
104 |
- ((h >> 7) & 0x02) | ((h >> 3) & 0x40); |
105 |
- /* line compare to 1023 */ |
106 |
- s->cr[VGA_CRTC_LINE_COMPARE] = 0xff; |
107 |
- s->cr[VGA_CRTC_OVERFLOW] |= 0x10; |
108 |
- s->cr[VGA_CRTC_MAX_SCAN] |= 0x40; |
109 |
- |
110 |
- if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) { |
111 |
- shift_control = 0; |
112 |
- s->sr[VGA_SEQ_CLOCK_MODE] &= ~8; /* no double line */ |
113 |
- } else { |
114 |
- shift_control = 2; |
115 |
- /* set chain 4 mode */ |
116 |
- s->sr[VGA_SEQ_MEMORY_MODE] |= VGA_SR04_CHN_4M; |
117 |
- /* activate all planes */ |
118 |
- s->sr[VGA_SEQ_PLANE_WRITE] |= VGA_SR02_ALL_PLANES; |
119 |
- } |
120 |
- s->gr[VGA_GFX_MODE] = (s->gr[VGA_GFX_MODE] & ~0x60) | |
121 |
- (shift_control << 5); |
122 |
- s->cr[VGA_CRTC_MAX_SCAN] &= ~0x9f; /* no double scan */ |
123 |
} else { |
124 |
/* XXX: the bios should do that */ |
125 |
s->bank_offset = 0; |
126 |
-- |
127 |
1.9.1 |
128 |
|